In the fabrication of semiconductor devices, source/drain contacts need to be formed which connect to their corresponding source/drain regions. The methods for forming self-aligned contacts that have been used up to now are facing a major challenge from the 10 nm node downwards. The high aspect ratio etching (e.g. 15:1 or larger) that is used to form the contacts, while maintaining a high etch selectivity (typically with respect to SiCO or SiN), appears to be at least impractical to achieve. As such, issues of underetching and/or overetching can easily happen within a die.
Furthermore, as technology scales down to the 10 nm node and lower, the issue of maximizing the contact area to a source/drain region, thereby keeping the contact and fin resistance within acceptable limits, becomes increasingly relevant. As such, wrap-around contacts appear to be the promising contact scheme to replace the diamond-shaped source/drain regions that are typically used up to now. However, the post-etch cleaning of the source/drain regions, e.g. epitaxially grown Si:P and SiGe:B, in complementary metal oxide semiconductor (CMOS) technology is challenging in practice.
U.S. Pat. No. 9,685,374B1 describes a method for making a semiconductor structure, comprising forming wrap-around contacts. However, the remote plasma etch used therein is difficult to control. Furthermore, the contact etch stop layer (CESL) is exposed twice to a selective etch, as such the CESL will need to be relatively thick (>5 nm). Both these issues make that this method is not well suited for small contacts; for example the 10 nm node, but more particularly the 7 nm node, where the contact critical dimension may typically be around 14 to 16 nm.
There is thus still a need in the art for better ways to form source/drain contacts in semiconductor structures.